State retained dual‐ V th feedback sleeper‐stack for leakage reduction-Reference-Cited by-同舟云学术

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State retained dual‐ V th feedback sleeper‐stack for leakage reduction

Published:2018-12-03 Issue:1 Volume:13 Page:1-10
ISSN:1751-8601
Container-title:IET Computers & Digital Techniques
language:en
Short-container-title:IET Computers & Digital Techniques

Author:

Sreekala Kollaparampil Somasekharan¹,Krishnakumar Sukumarapillai¹

Affiliation:

1. Department of ElectronicsSchool of Technology and Applied SciencesMahatma Gandhi University AffiliatedEdappallyKochiKeralaIndia

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cdt.2018.0009

Reference33 articles.

1. Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

2. Anjana R. Kumar Somkuwar A.: ‘Analysis of sub threshold leakage reduction techniques in deep sub micron regime for CMOS VLSI circuits’.Proc. IEEE Int. Conf. on Emerging Trends in VLSI Embedded System Nano Electronics and Telecommunication System Tiruvannamalai India January2013 pp.1–5

3. Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells

4. Analysis of leakage currents and impact on off-state power consumption for CMOS technology in the 100-nm regime

5. Estimation of leakage power and delay in CMOS circuits using parametric variation;Verma P.;Perspect. Sci.,2016

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