Embedding of signatures in reconfigurable scan architecture for authentication of intellectual properties in system‐on‐chip-Reference-Cited by-同舟云学术

Embedding of signatures in reconfigurable scan architecture for authentication of intellectual properties in system‐on‐chip

Published:2016-05 Issue:3 Volume:10 Page:110-118
ISSN:1751-8601
Container-title:IET Computers & Digital Techniques
language:en
Short-container-title:IET Computers & Digital Techniques

Author:

Saha Debasri¹,Sur‐Kolay Susmita²

Affiliation:

1. A.K. Choudhury School of Information TechnologyUniversity of CalcuttaKolkataIndia

2. Advanced Computing & Microelectronics UnitIndian Statistical InstituteKolkataIndia

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cdt.2015.0051

Reference18 articles.

1. Constraint‐based watermarking techniques for design IP protection;Kahng A.B.;IEEE Trans. CAD Integr. Circuits Syst.,2001

2. Alkabani Y. Koushanfar F. Potkonjak M.: ‘Remote activation of ICs for privacy prevention and digital right management’.Proc. Int. Conf. on Computer‐Aided Design (ICCAD) 2007 pp.674–677

3. Huang J. Lach J.: ‘IC activation and user authentication for security‐sensitive systems’.Proc. Int. Symp. on Hardware‐Oriented Security and Trust 2008 pp.76–80

4. HARPOON: an obfuscation‐based SOC design methodology for hardware protection;Chakraborty R.S.;IEEE Trans. CAD Integr. Circuits Syst.,2009

5. Techniques for design and implementation of secure reconfigurable PUFs;Majzoobi M.;ACM Trans. Reconfigurable Technol. Syst.,2009

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Criticality based Reduction of Security Costs in a FPGA based Cloud Computing Farm;2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID);2021-02

2. Introduction to Hardware Security for FPGA Based Systems;Self Aware Security for Real Time Task Schedules in Reconfigurable Hardware Platforms;2021

3. Dynamic power-aware scheduling of real-time tasks for FPGA-based cyber physical systems against power draining hardware trojan attacks;The Journal of Supercomputing;2020-02-13

4. A Multi-Agent Co-operative Model to Facilitate Criticality based Reliability for Mixed Critical Task Execution on FPGA based Cloud Environment;2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID);2020-01

5. Criticality based reliability against hardware Trojan attacks for processing of tasks on reconfigurable hardware;Microprocessors and Microsystems;2019-11