Design of a novel energy efficient topology for maximum magnitude generator-Reference-Cited by-同舟云学术

Design of a novel energy efficient topology for maximum magnitude generator

Published:2016-05 Issue:3 Volume:10 Page:93-101
ISSN:1751-8601
Container-title:IET Computers & Digital Techniques
language:en
Short-container-title:IET Computers & Digital Techniques

Author:

Kathirvel Swaminathan¹²,Jangre Rajkumar³,Ko Seokbum¹

Affiliation:

1. Department of Electrical and Computer EngineeringUniversity of SaskatchewanSaskatoonCanada

2. Silicic Innova Technologies Pvt LtdTiruchirapalliIndia

3. S3Craft Technologies Private LimitedBengaluruIndia

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cdt.2015.0066

Reference27 articles.

1. Yuce B. Ugurdag H. Goren S. et al.: ‘A fast circuit topology for finding the maximum of N k‐bit numbers’.IEEE 21st Symposium on Computer Arithmetic 2013 pp.59–66

2. Fast and efficient circuit topologies for finding the maximum of n k‐Bit numbers;Yuce B.;IEEE Trans. Comput.,2014

3. Yang M. Zheng S. Bhagyavati B. et al.: ‘Programmable weighted arbiters for constructing switch schedulers’.Workshop on High Performance Switching and Routing 2004 pp.203–206

4. Azuma S. Sakuma T. Nakano T. et al.: ‘High‐performance sort chip’.A Symp. on High Performance Chips 1999

5. On the complexity of min–max sorting networks

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