Power efficient error correction coding for on‐chip interconnection links-Reference-Cited by-同舟云学术

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Power efficient error correction coding for on‐chip interconnection links

Published:2020-10 Issue:6 Volume:14 Page:299-312
ISSN:1751-8601
Container-title:IET Computers & Digital Techniques
language:en
Short-container-title:IET Computers & Digital Techniques

Author:

Velayudham Sumitra¹^ORCID,Rajagopal Sivakumar²,Venkata Ramana Rao Yeragudipati³,Ko Seok‐Bum⁴

Affiliation:

1. Department of ECER. M. K. Engineering CollegeChennai601 206India

2. Department of Sensor and Biomedical TechnologySENSE, VITVellore632 014India

3. Department of ECECollege of Engineering, GuindyChennai600 025India

4. Department of Electrical and Computer EngineeringUniversity of SaskatchewanSaskatoonCanadaS7N 5A9

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cdt.2019.0082

Reference51 articles.

1. Design and verification of an efficient WISHBONE‐based network interface for network on chip;Swaminathan K.;Comput. Electr. Eng.,2014

2. Coding for system-on-chip networks: a unified framework

3. Design of a novel error correction coding with crosstalk avoidance for reliable on‐chip interconnection link;Maheswari M.;Int. J. Comput. Appl. Technol.,2014

4. The challenge of signal integrity in deep‐submicrometer CMOS technology;Caignet F.;Proc. IEEE,2001

5. Analytical modeling and characterization of deep-submicrometer interconnect

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2. Implementation of Novel Block and Convolutional Encoding Circuit Using FS-GDI;IETE Journal of Research;2023-03-15

3. Memory Optimized Hardware Implementation of Open FEC Encoder;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2022-10

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