A Fast Circuit Topology for Finding the Maximum of N k-bit Numbers

Author:

Yuce B.,Ugurdag H. F.,Goren S.,Dundar G.

Publisher

IEEE

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Modified Rejection-Based Architecture to Find the First Two Minima in Min-Sum-Based LDPC Decoders;2020 IEEE Wireless Communications and Networking Conference (WCNC);2020-05

2. A fast method for particle tracking and triggering using small-radius silicon detectors;Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment;2020-03

3. Hardware Accelerators for Data Sort;Lecture Notes in Electrical Engineering;2019

4. Design of a novel energy efficient topology for maximum magnitude generator;IET Computers & Digital Techniques;2016-05

5. Feature-rich Regular Expression Matching Accelerator for Text Analytics;Journal of Signal Processing Systems;2015-10-09

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