Low‐cost single event double‐upset tolerant latch design-Reference-Cited by-同舟云学术

Low‐cost single event double‐upset tolerant latch design

Published:2018-05 Issue:9 Volume:54 Page:554-556
ISSN:0013-5194
Container-title:Electronics Letters
language:en
Short-container-title:Electron. lett.

Author:

Jiang Jianwei¹,Xu Yiran¹,Ren Jiangchuan¹,Zhu Wenyi¹,Lin Dianpeng¹,Xiao Jun²,Kong Weiran²,Zou Shichang¹

Affiliation:

1. State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of SciencesShanghai200050People's Republic of China

2. Shanghai Huahong Grace Semiconductor Manufacturing CorporationShanghai201203People's Republic of China

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2018.0558

Reference8 articles.

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2. High performance, low cost, and robust soft error tolerant latch designs for nanoscale CMOS technology;Nan H.;Trans. Circuits Syst. I, Regul. Pap.,2012

3. Physics of multiple‐node charge collection and impacts on single‐event characterization and soft error rate prediction;Black J.;Trans. Nucl. Sci.,2013

4. Schemes for eliminating transient width clock overhead from set‐tolerant memory‐based systems;Blum D.R.;Trans. Nucl. Sci.,2006

5. Soft error interception latch: double node charge sharing SEU tolerant design

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