Fast split background calibration for pipelined ADCs enabled by slope mismatch averaging technique
Author:
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://digital-library.theiet.org/content/journals/10.1049/el.2012.0357?crawler=true&mimetype=application/pdf
Reference5 articles.
1. "Split ADC" architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC
2. Digital Background Correction of Harmonic Distortion in Pipelined ADCs
3. Background Calibration of Pipelined ADCs Via Decision Boundary Gap Estimation
4. A 12-Bit 200-MHz CMOS ADC
5. An 11-Bit 45 MS/s Pipelined ADC With Rapid Calibration of DAC Errors in a Multibit Pipeline Stage
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2. Digital calibration of pipelined ADC using Newton–Raphson algorithm;Analog Integrated Circuits and Signal Processing;2020-05-08
3. Digital Background Calibration of a Split Current-Steering DAC;IEEE Transactions on Circuits and Systems I: Regular Papers;2019-08
4. A Split-Based Digital Background Calibration of Pipelined Analog-to-Digital Converters by Cubic Spline Interpolation Filtering;Circuits, Systems, and Signal Processing;2019-03-13
5. A 66-dB SNDR Pipelined Split-ADC in 40-nm CMOS Using a Class-AB Residue Amplifier;IEEE Journal of Solid-State Circuits;2018-10
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