A Split-Based Digital Background Calibration of Pipelined Analog-to-Digital Converters by Cubic Spline Interpolation Filtering
Author:
Publisher
Springer Science and Business Media LLC
Subject
Applied Mathematics,Signal Processing
Link
http://link.springer.com/content/pdf/10.1007/s00034-019-01090-5.pdf
Reference20 articles.
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2. I. Ahmed, D.A. Johns, An 11-bit 45 MS/s pipelined ADC with rapid calibration of DAC errors in a multibit pipeline stage. IEEE J. Solid-State Circuits 43, 1626–1637 (2008). https://doi.org/10.1109/JSSC.2008.923724
3. C. DeBoor, A Practical Guide to Splines (Springer, New York, 1978). https://doi.org/10.2307/2006241
4. P. Gholami, M. Yavari, Digital background calibration with histogram of decision points in pipelined ADCs. IEEE Trans. Circuits Syst. II Exp. Briefs 65, 16–20 (2017). https://doi.org/10.1109/TCSII.2017.2660765
5. J.K.R. Kim, B. Murmann, A 12-b, 30-MS/s, 2.95-mW pipelined ADC using single-stage class-AB amplifiers and deterministic background calibration. IEEE J. Solid-State Circuits 47, 2141–2151 (2012). https://doi.org/10.1109/JSSC.2012.2194191
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