Generating test patterns for VLSI circuits using a genetic algorithm
Author:
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://digital-library.theiet.org/content/journals/10.1049/el_19940524?crawler=true&mimetype=application/pdf
Reference8 articles.
1. Lala, P.K.: ‘Fault tolerant & fault testable hardware design’, (Prentice/Hall International London 1985)
2. Russell, G., Kinniment, D.J., Chester, E.G., and McLauchlan, M.R.: ‘CAD for VLSI’, (Van Nostrand Reinhold UK 1985)
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