A method for fault recognition in the last three rounds of Advanced Encryption Standard-Reference-Cited by-同舟云学术

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A method for fault recognition in the last three rounds of Advanced Encryption Standard

Published:2021-04-22 Issue:13 Volume:57 Page:511-513
ISSN:0013-5194
Container-title:Electronics Letters
language:en
Short-container-title:Electron. lett.

Author:

Jiang Huilong¹²^ORCID,Zhu Xiang¹²^ORCID,Pang Jinfeng³,Liu Zhipeng³,Han Jianwei¹²,Li Yue¹

Affiliation:

1. Space Environment Effects Laboratory National Space Science Center Chinese Academy of Sciences Beijing China

2. School of Astronomy and Space Science University of Chinese Academy of Sciences Beijing China

3. College of Internet of Things Engineering Hohai University Nanjing China

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/ell2.12188

Reference5 articles.

1. Global Faults on Cryptographic Circuits

2. Agoyan M. et al.:When clocks fail: On critical paths and clock faults. In:International Conference on Smart Card Research and Advanced Applications Passau pp.182–193(2010)

3. Torrance R. James D.:The state‐of‐the‐art in IC reverse engineering. In:International Workshop on Cryptographic Hardware and Embedded Systems Lausanne pp.363–381(2009)

4. Mukhopadhyay D.:An improved fault based attack of the Advanced Encryption Standard. In:International Conference on Cryptology in Africa Gammarth pp.421–434(2009)

5. Dusart P. Letourneux G. Vivolo O.:Differential fault analysis on AES. In:International Conference on Applied Cryptography and Network Security Kunming pp.293–306(2003)

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