The State-of-the-Art in IC Reverse Engineering-Reference-Cited by-同舟云学术

The State-of-the-Art in IC Reverse Engineering

Published:2009 Issue: Volume: Page:363-381
ISSN:0302-9743
Container-title:Lecture Notes in Computer Science
language:
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Author:

Torrance Randy,James Dick

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/978-3-642-04138-9_26

Reference6 articles.

1. James, D.: A Case Study: Looking Inside Apple’s iPOD Nano– a Teardown to the Atomic Scale, http://electronics.wesrch.com/Paper/paper_details.php?id=EL1SE1KWRX174&paper_type=pdf&type=author

2. Nii, H., et al.: A 45 nm High Performance Bulk Logic Platform Technology (CMOS6) using Ultra High NA (1.07) Immersion Lithography with Hybrid Dual-Damascene Structure and Porous Low-k BEOL. In: IEDM 2006 Technical Digest, pp. 685–688 (2006)

3. Narasimha, S., et al.: High Performance 45 nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography. In: IEDM 2006 Technical Digest, pp. 689–692 (2006)

4. Chatterjee, A., et al.: A 65 nm CMOS Technology for Mobile and Digital Signal Processing Applications. In: IEDM 2004 Technical Digest, pp. 665–668 (2004)

5. 2005 ITRS, Metrology section

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