Fully monolithic integrated 43 Gbit/s clock and data recovery circuit in InP HEMT technology
Author:
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://digital-library.theiet.org/content/journals/10.1049/el_20010837?crawler=true&mimetype=application/pdf
Reference9 articles.
1. ‘Interface for optical transport network (OTN)’, ITU-T recommendation G.709, 2001
2. 3.5-Gb/s×4-ch Si bipolar LSI's for optical interconnections
3. A monolithic 156 Mb/s clock and data recovery PLL circuit using the sample-and-hold technique
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1. Design and Implementation of Open-Loop Clock Recovery Circuit for 39.8 Gb/s and 42.8 Gb/s Dual-Mode Operation;ETRI Journal;2008-04-08
2. InP DHBT-Based Monolithically Integrated CDR/DEMUX IC Operating at 80 Gbit/s;IEEE Journal of Solid-State Circuits;2006-10
3. IC Technologies for Future Lightwave Communication Systems;High-Speed Photonic Devices;2006-09-29
4. A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector;IEEE Journal of Solid-State Circuits;2004-08
5. A 43-Gb/s Clock and Data Recovery OEIC Integrating an InP–InGaAs HPT Oscillator with an HBT Decision Circuit;IEEE Journal of Selected Topics in Quantum Electronics;2004-07
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