A monolithic 156 Mb/s clock and data recovery PLL circuit using the sample-and-hold technique
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx1/4/7973/00340432.pdf?arnumber=340432
Cited by 14 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
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