High performance 5 : 2 compressor architectures
Author:
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://digital-library.theiet.org/content/journals/10.1049/ip-cds_20050152?crawler=true&mimetype=application/pdf
Reference12 articles.
1. Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology
2. Circuit and architecture trade-offs for high-speed multiplication
3. TWTXBB: a low latency, high throughput multiplier architecture using a new 4→2 compressor
Cited by 20 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Design and Implementation of Hybrid Full Adder Based 16-bit Multiplication Using FPGA;2023 IEEE Devices for Integrated Circuit (DevIC);2023-04-07
2. FPGA Implementation of Area Efficient 16-Bit Vedic Multiplier Using Higher Order Compressors;2023 IEEE Devices for Integrated Circuit (DevIC);2023-04-07
3. Design and Implementation of Array Multiplier using Compressor for Low Power;2022 International Conference for Advancement in Technology (ICONAT);2022-01-21
4. Optimized Image Multiplication with Approximate Counter Based Compressor;Computers, Materials & Continua;2022
5. High-Performance Wallace Tree Multiplier Design Using Novel 8-4 Compressor Implementation for Image Processing;Proceedings of First International Conference on Computational Electronics for Wireless Communications;2022
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