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The optimal design of 15 nm gate-length junctionless SOI FinFETs for reducing leakage current

  • Published:2013-08-16 Issue:10 Volume:28 Page:105013
  • ISSN:0268-1242
  • Container-title:Semiconductor Science and Technology
  • language:
  • Short-container-title:Semicond. Sci. Technol.

Author:

Liu Xi,Wu Meile,Jin Xiaoshi,Chuai Rongyan,Lee Jung-Hee,Lee Jong-Ho

Publisher

IOP Publishing

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Performance optimization of tri-gate junctionless FinFET using channel stack engineering for digital and analog/RF design;Journal of Semiconductors;2023-11-01

2. Design and Analysis of Electrical Characteristics of 14nm SOI-based Trigate Gaussian Channel Junctionless FinFET;Journal of Physics: Conference Series;2023-10-01

3. Performance Analysis of 14nm SOI-based Trigate Gaussian Channel Junctionless FinFET with Punchthrough Stop Layer;2023 IEEE Regional Symposium on Micro and Nanoelectronics (RSM);2023-08-28

4. A novel high-performance fold I shaped junctionless FinFET;International Journal of Electronics Letters;2019-06-23

5. A novel low leakage saddle junctionless FET with assistant gate;International Journal of Numerical Modelling: Electronic Networks, Devices and Fields;2018-06-14
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