Design and performance analysis of GaN vertical JFETs with ion-implanted gates

Abstract

Abstract We present a comprehensive performance analysis of vertical GaN JFETs via TCAD simulation with unique considerations for gates formed by Mg ion implantation into GaN. The dependence of the specific ON-resistance and pinch-off voltage on the gate and channel design parameters is first evaluated for a JFET with abrupt gate-channel junctions. Then, the influence of the gate acceptor concentration and distribution is studied to elucidate the consequences of incomplete acceptor activation or acceptor diffusion resulting from specialized post-implantation annealing techniques necessary for the activation of p-GaN. Examples of normally-ON and normally-OFF designs with 1.7 kV breakdown voltage for 1.2 kV applications are chosen for the activation and diffusion studies to demonstrate how the pinch-off and conduction characteristics are affected for different channel widths and doping concentrations conducive to each type of operation. Record low specific ON-resistance below 1 mΩ cm2 is predicted for both, but gate acceptor diffusion increases the channel resistance, especially for JFETs designed to be normally-OFF.