A 2-D compact DC model for engineered nanowire JAM-MOSFETs valid for all operating regimes-Reference-Cited by-同舟云学术

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A 2-D compact DC model for engineered nanowire JAM-MOSFETs valid for all operating regimes

Published:2020-07-06 Issue:8 Volume:35 Page:085014
ISSN:0268-1242
Container-title:Semiconductor Science and Technology
language:
Short-container-title:Semicond. Sci. Technol.

Author:

Baral Kamalaksha,Singh Prince Kr,Kumar Sanjay,Tripathy Manas Ranjan,Singh Ashish Kr,Chander Sweta,Jit S^ORCID

Publisher

IOP Publishing

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://iopscience.iop.org/article/10.1088/1361-6641/ab8fc0/pdf

Reference33 articles.

1. Nanowire transistors without junctions

2. RF performance of ultra low power junctionless MOSFETs

3. Modeling Nanowire and Double-Gate Junctionless Field-Effect Transistors

4. Analytical modeling simulation and characterization of short channel Junctionless Accumulation Mode Surrounding Gate (JLAMSG) MOSFET for improved analog/RF performance

5. Insight into Lateral Band-to-Band-Tunneling in Nanowire Junctionless FETs

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Modeling threshold voltage and drain-induced barrier lowering effect of opposite doping core–shell channel surrounding-gate junctionless MOSFET;Microelectronics Journal;2023-09

2. A unified 2-D model for nanowire junctionless accumulation and inversion mode MOSFET in quasi-ballistic regime;Solid-State Electronics;2022-07

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