Enhancement of Ge-based p-channel vertical FET performance by channel engineering using planar doping and a Ge/Si x Ge1–x–y Sn y heterostructure model for low power FET applications-Reference-Cited by-同舟云学术

Enhancement of Ge-based p-channel vertical FET performance by channel engineering using planar doping and a Ge/Si x Ge1–x–y Sn y heterostructure model for low power FET applications

Published:2018-10-04 Issue:11 Volume:33 Page:114001
ISSN:0268-1242
Container-title:Semiconductor Science and Technology
language:
Short-container-title:Semicond. Sci. Technol.

Author:

Elogail Yasmine^ORCID,Fischer Inga A,Wendav Torsten,Schulze Jörg

Publisher

IOP Publishing

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

http://iopscience.iop.org/article/10.1088/1361-6641/aae001/pdf

Reference44 articles.

1. Experimental comparison between relaxed and strained Ge pFinFETs

2. Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition

3. Performance and electrostatic improvement by high-pressure anneal on Si-passivated strained Ge pFinFET and gate all around devices with superior NBTI reliability

4. Demonstration of Ge Nanowire CMOS Devices and Circuits for Ultimate Scaling

5. Fully Depleted Ge CMOS Devices and Logic Circuits on Si

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