Theoretical and experimental investigations of barrier height inhomogeneities in poly-Si/4H-SiC heterojunction diodes

Abstract

Abstract p-Si/4H-SiC heterojunction diodes are realized by sputter-deposition of the Si top contact and subsequent post-deposition annealing at either 900 °C or 1000 °C. The high Schottky barrier height (SBH) of this junction architecture of around 1.65 V is ideal to analyze SBH inhomogeneities present in most Schottky- and heterojunctions. Current-voltage-temperature (IVT) and capacitance-voltage-temperature (CVT) measurements are conducted in a wide temperature range from 60 K up to 460 K while applying standard techniques for SBH extraction. Strong deviations from ideal IV characteristics are present especially at lowest temperatures when assuming a homogenous SBH. Additionally, the extracted SBHs at low temperatures differ a lot between the two methods, indicating the presence of low barrier conduction paths. The presence of at least two distinct SBH inhomogeneities is found, which are labeled as ‘intrinsic’ and ‘extrinsic’. Next, the Tung model was applied to fit the measured IVT data using a discretized Gaussian distribution of patch parameters to account for spreading resistance effects. By using multiple Gaussian distributions, excellent fitting results were achieved, giving the density values of the different patches and a background barrier height from the IVT data, which are in excellent agreement with the CVT data over a wide temperature range of 400 K.