Investigation on performance degradation due to induced interface trapped charges on HSO based FDSOI NCFET and sustaining it through back-gate bias

Abstract

Abstract In this article, a variant of doped HfO2 based ferroelectric capacitor i.e. silicon doped HfO2 (hafnia-silica/HSO) is investigated for analytical feasibility and viability for negative capacitance FET (NCFET) applications. Investigations are carried out extensively using well calibrated and validated numerical simulations to find out the optimum ferroelectric thickness (tf) of HSO thin-film for the NCFET to operate in hysteresis-free regime. The optimized NCFET is then subjected to the variation of back-gate bias (V B ) to exploit threshold-voltage ( V T H ) shift phenomena might further improve NCFET performance. In continuance, the optimized NCFET has been introduced with interface trap (+Nit) charges at the oxide–semiconductor interface to emphasize on the reliability deflation caused at process level design. Hence, this has allowed us to concisely observe and analyse performance degradation aspect of the NCFET with numerical simulations. Also, a feasibility to recuperate the degraded performance caused by +Nit with utilizing −V B is carried out. The performance metrics used in the numerical simulation for the evaluation of HSO ferroelectric NCFET are: sub-threshold slope, charge variation with gate-voltage and ferro voltage, surface potential, V T H , drain-current and amplification factor.