Barrier height tuning by inverse sputter etching at poly-Si/4H-SiC heterojunction diodes

Abstract

Abstract Si/4H-SiC heterojunction diodes (HJDs) are fabricated by applying Ar+ inverse sputter etching (ISE) of the 4H-SiC substrate prior to Si deposition. A subsequent annealing step was used to crystallize the sputter deposited amorphous Si. Numerical simulations and experiments were conducted to investigate the amorphization depth and etch rate of low energy Ar+ ions on the Si-face of 4H-SiC. Electrical characterization of the HJDs showed a strong influence of the ISE treatment in both n and p-type Si contacts compared to untreated diodes. The ISE power, as well as the ISE time can be tailored to adjust the Schottky barrier height (SBH) in a certain range, by simultaneously improving the device ideality for most ISE parameters compared to diodes without any ISE treatment. In addition, the homogeneity of the SBHs is improved, resulting in less variation over temperature and between different samples. The formation of a smooth Si–SiC transition region instead of a sharp interface is found after both ISE treatment and thermal annealing.