Design of Compact and Smart Full Adders for High-Speed Nanometer Technology IC’s

Abstract

Abstract It is intensely acknowledged that the key handing out unit of any device competent of carrying out computations is the CPU (Central Processing Unit) and one of the most elementary and central parts of CPU is an ALU (Arithmetic and Logical Unit). The ALU is primarily responsible for carrying out the logical operation, arithmetic operations etc. The proposed full adder has low power consumption and better area efficiency. Post layout simulations using the Mentor graphics tool have been evaluated. The circuits proposed are extremely optimize in terms of transitor switching power and latency, due to small load capacitance and low dissipation of short circuit electricity. Each of the suggested and simulated circuits has its own benefits of speed, power Dissipation, Power Delay Product (PDP), and driving capability. The circuits proposed are studied in terms of voltage input and threshold voltage variations, output load variations, signal to ratio with respect to transistor scaling.