Analysis and Design of Low Power Consumption 8T and 10T Full Adder CMOS Technology-Reference-Cited by-同舟云学术

Analysis and Design of Low Power Consumption 8T and 10T Full Adder CMOS Technology

Published:2022-10-12 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE 13th Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON)
language:
Short-container-title:

Author:

Bin Abd Majid Mohamed Ibrahim¹,Sahak Rohilah²,Subramaniam Krishnan¹,Zainuddin Ahmad Anwar³,Rahman Siti Husna Abdul⁴,Puzi Asmarani Ahmad³,Mansor Ahmad Fairuzabadi Mohd³,Yunos Muhammad Farhan Affendi Mohamad³,Svpk Satya Devu¹

Affiliation:

1. Manipal International University,Negeri Sembilan,Malaysia

2. Silverseeds Lab Network,Gombak,Malaysia

3. International Islamic University,Malaysia,Malaysia

4. Multimedia University,Faculty of Computing & Informatics (FCI),Cyberjaya,Malaysia

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9946385/9946450/09946570.pdf?arnumber=9946570

Reference26 articles.

1. Simulation of Low-Power Shift Registers Using the MTCMOS Method with a Wide Selection of Transistors

2. Power reduction in full adder using new hybrid logic;kayathri;International Journal of Current Research and Modern Education (IJCRME),2016

3. Design and Analysis of Low Power Full Adder;palaniappan;International Journal of Advanced Research Trends in Engineering and Technology (IJARTET),2017

4. Analysis and performance evalution of I-bit full adder using different topologies;wilson;International Journal of Engineering Research and General Science,2017

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Implementation of 1-bit Full Adder using Various Low Power Techniques on 45nm Technology;2023 9th International Conference on Signal Processing and Communication (ICSC);2023-12-21