Negative differential resistance in Si nanostructure: role of interface traps

Abstract

Abstract Negative differential resistance (NDR) has been observed in I-V characteristics measured between two aluminum (Al) pads deposited on a layer containing Silicon nanostructures. This feature has been observed for suitable bias range and specific direction of voltage sweep. NDR has been found to show up within a specific range of lower and upper threshold voltages for each of the samples studied in this work. The amount of NDR has been found to depend on voltage scan rate and bias range. The observed phenomena have been explained using the dynamics of charge trapping and detrapping at the surface/interface defect states present at the boundary of the nanostructured silicon and the oxide layer. An equivalent circuit designed by incorporation of suitable resistance and capacitance representing the trap assisted charge transport within the aluminum-Silicon nanostructure junctions has produced similar I-V characteristics as obtained in the experimental results. Repeatability of NDR shows the potential of the device to be used in oscillators.