Exploration of effects of gate underlap in HOI FinFETs at 10 nm gate length

Abstract

Abstract With sub-22 nm technology nodes, the short channel effects (SCEs) arose in FinFETs, which hindered the further scaling of devices. The leakage currents became detrimental with scaling of the gate oxide thickness below 2 nm, hence the demand for control of leakage currents due to corner effects in the sidewalls of FinFETs. Research suggested use of gate underlap (GUL) architectures to suppress the leakage currents. The objective of this paper is to utilize a GUL structure in a 10 nm gate length Heterostructure-On-Insulator (HOI) FinFET, encompassing a three layered strained channel architecture to enrich the drive currents. Different structures with GUL lengths of 1 nm, 3 nm and 5 nm are designed to study the electrical characteristics besides the effects of leakage currents and other SCEs. A noteworthy decrease is observed in the leakage currents with increasing GUL lengths. However, it also leads to decrease of drive currents of the devices. A trade-off between the enhanced dimensions of source/drain along with an optimized GUL length proves beneficial in the strained silicon channel devices. The 10 nm HOI device employing a 3 nm GUL with height/width of source/drain at 8 nm provides drive currents and leakage currents at par with the 10 nm HOI device with no underlap. But with higher Ion/Ioff current ratio and lower SCEs, this device with 3 nm underlap decreases corner effects and is observed from the electron velocity and total current density contours leading to faster switching speeds and optimized device performance towards semiconductor industry.