Author:
Zambito S.,Milanesio M.,Moretti T.,Paolozzi L.,Munker M.,Cardella R.,Kugathasan T.,Martinelli F.,Picardi A.,Elviretti M.,Rücker H.,Trusch A.,Cadoux F.,Cardarelli R.,Débieux S.,Favre Y.,Fenoglio C.A.,Ferrere D.,Gonzalez-Sevilla S.,Iodice L.,Kotitsa R.,Magliocca C.,Nessi M.,Pizarro-Medina A.,Sabater Iglesias J.,Saidi J.,Vicente Barreto Pinto M.,Iacobucci G.
Abstract
Abstract
A second monolithic silicon pixel prototype was produced for
the MONOLITH project. The ASIC contains a matrix of hexagonal pixels
with 100 μm pitch, readout by a low-noise and very fast SiGe HBT
frontend electronics. Wafers with 50 μm thick epilayer of
350 Ωcm resistivity were used to produce a fully depleted
sensor. Laboratory and testbeam measurements of the analog channels
present in the pixel matrix show that the sensor has a 130 V wide
bias-voltage operation plateau at which the efficiency is 99.8%.
Although this prototype does not include an internal gain layer, the
design optimised for timing of the sensor and the front-end
electronics provides a time resolutions of 20 ps.
Subject
Mathematical Physics,Instrumentation
Cited by
5 articles.
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