Improvement on short-circuit ability of SiC super-junction MOSFET with partially widened pillar structure

Abstract

A novel 1200 V SiC super-junction (SJ) MOSFET with a partially widened pillar structure is proposed and investigated by using the two-dimensional numerical simulation tool. Based on the SiC SJ MOSFET structure, a partially widened P-region is added at the SJ pillar region to improve the short-circuit (SC) ability. After investigating the position and doping concentration of the widened P-region, an optimal structure is determined. From the simulation results, the SC withstand times (SCWTs) of the conventional trench MOSFET (CT-MOSFET), the SJ MOSFET, and the proposed structure at 800 V DC bus voltage are 15 μs, 17 μs, and 24 μs, respectively. The SCWTs of the proposed structure are increased by 60% and 41.2% in comparison with that of the other two structures. The main reason for the proposed structure with an enhanced SC capability is related to the effective suppression of saturation current at the high DC bias conditions by using a modulated P-pillar region. Meanwhile, a good Baliga’s FOM (BV 2/R on) also can be achieved in the proposed structure due to the advantage of the SJ structure. In addition, the fabrication technology of the proposed structure is compatible with the standard epitaxy growth method used in the SJ MOSFET. As a result, the SJ structure with this feasible optimization skill presents an effect on improving the SC reliability of the SiC SJ MOSFET without the degeneration of the Baliga’s FOM.