An ultra-low specific on-resistance trench LDMOS with a U-shaped gate and accumulation layer
Author:
Publisher
IOP Publishing
Subject
General Physics and Astronomy
Link
https://iopscience.iop.org/article/10.1088/1674-1056/24/4/047304/pdf
Reference13 articles.
1. Simulated superior performances of semiconductor superjunction devices
2. Low Specific on-Resistance Power MOS Transistor With Multilayer Carrier Accumulation Breaks the Limit Line of Silicon
3. A review of RESURF technology
4. A new 800 V lateral MOSFET with dual conduction paths
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1. Terminal-optimized 700-V LDMOS with improved breakdown voltage and ESD robustness*;Chinese Physics B;2021-06-01
2. Modeling electric field of power metal-oxide-semiconductor field-effect transistor with dielectric trench based on Schwarz–Christoffel transformation*;Chinese Physics B;2019-05-01
3. Low Specific On-Resistance SOI LDMOS with Non-Depleted Embedded P-Island and Dual Trench Gate;Chinese Physics Letters;2018-03
4. A novel high performance LDMOS transistor with high channel density;Journal of Computational Electronics;2017-09-15
5. A novel high voltage LDMOS with body depletion termination;International Journal of Electronics Letters;2017-06-03
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