Improving robustness of GGNMOS with P-base layer for electrostatic discharge protection in 0.5- μ m BCD process

Abstract

Gate-grounded N-channel MOSFET (GGNMOS) has been extensively used for on-chip electrostatic discharge (ESD) protection. However, the ESD performance of the conventional GGNMOS is significantly degraded by the current crowding effect. In this paper, an enhanced GGNMOS with P-base layer (PB-NMOS) are proposed to improve the ESD robustness in BCD process without the increase in layout area or additional layer. TCAD simulations are carried out to explain the underlying mechanisms of that utilizing the P-base layer can effectively restrain the current crowing effect in proposed devices. All devices are fabricated in a 0.5- μ m BCD process and measured using the transmission line pulsing (TLP) tester. Compared with the conventional GGNMOS, the proposed PB-NMOS devices offer a higher failure current than its conventional counterpart, which can be increased by 15.38%. Furthermore, the PB-NMOS_type3 possesses a considerably lower trigger voltage than the conventional GGNMOS to protect core circuit effectively.