The effect of PCB surface finish on lead‐free solder joints

Author:

Nurmi Sami T.,Sundelin Janne J.,Ristolainen Eero O.,Lepistö Toivo K.

Abstract

PurposeTo study the behaviour of voids in PBGA solder joints and their influence on the lifetime of lead‐free solder joints.Design/methodology/approachThe behaviour of voids was studied using micro via and land pad PWBs, PBGA components, and by measuring voids in the solder joints. The lifetimes of solder joints were tested using accelerated temperature tests.FindingsNumber of factors affecting the solder joint lifetimes were found. The voids were discovered to have a significantly large influence on the solder joints.Practical implicationsThe findings can be used to achieve better soldering results, methods, and designs.Originality/valueIn this paper, the effect and the behaviour of voids were studied profoundly. The findings can be valuable to researchers and process personnel.

Publisher

Emerald

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,General Materials Science,Electrical and Electronic Engineering,Condensed Matter Physics,General Materials Science

Reference24 articles.

1. Alander, T., Nurmi, S., Heino, P. and Ristolainen, E. (2002), “Impact of component placement in solder joint reliability”, Microelectronics Reliability, Vol. 42 No. 3, pp. 399‐406, Elsevier, Amsterdam.

2. Bailey, C., Lu, H. and Wheeler, D. (2000), “Predicting the movement of voids in solder bumps and subsequent reliability”, Proceedings of the 3rd IEEE/CPMT Electronics Packaging Technology Conference – EPTC 2000, Singapore, pp. 97‐102.

3. Casey, W. (1999), “Reduction of voiding in eutectic ball grid array solder joints”, Soldering & Surface Mount Technology, Vol. 11 No. 2, pp. 12‐16.

4. Chung, K., Mustapha, F., Hua, F. and Aspandiar, R. (2002), “An assessment of lead free solder (Sn3.7Ag0.8Cu) wettability”, Proceedings of the 4th IEEE Electronics Packaging Technology Conference, Kulim, Malaysia, pp. 1‐5.

5. Goenka, L. and Achari, A. (1995), “Void formation in flip‐chip solder bumps – part I”, Proceedings of the 17th IEEE/CPMT International Electronics Manufacturing Technology Symposium, Austin, pp. 14‐19.

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