Publisher
Cambridge University Press
Cited by
71 articles.
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1. Scan Design Using Unsupervised Machine Learning to Reduce Functional Timing and Area Impact;2024 IEEE European Test Symposium (ETS);2024-05-20
2. Built in self test (BIST) for RSFQ circuits;2024 IEEE 42nd VLSI Test Symposium (VTS);2024-04-22
3. Mirroring ATPG Technology for Multi-Core Chips;2024 Conference of Science and Technology for Integrated Circuits (CSTIC);2024-03-17
4. Design for testability (DFT) for RSFQ circuits;2023 IEEE 41st VLSI Test Symposium (VTS);2023-04-24
5. Conventional Methods for Fault Diagnosis;Machine Learning Support for Fault Diagnosis of System-on-Chip;2023