Design for testability (DFT) for RSFQ circuits
Author:
Affiliation:
1. University of Southern California,Department of Electrical Engineering,Los Angeles,CA,90089
Funder
Office of the Director of National Intelligence
Intelligence Advanced Research Projects Activity
Army Research Office
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10139918/10139926/10139966.pdf?arnumber=10139966
Reference15 articles.
1. Design for Testability of SFQ Circuits
2. Test point insertion for RSFQ circuits
3. Testing of Digital Systems
4. 13.1 A Fully Integrated Cryo-CMOS SoC for Qubit Control in Quantum Computers Capable of State Manipulation, Readout and High-Speed Gate Pulsing of Spin Qubits in Intel 22nm FFL FinFET Technology
5. An Effective and Efficient Automatic Test Pattern Generation (ATPG) Paradigm for Certifying Performance of RSFQ Circuits
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1. Built in self test (BIST) for RSFQ circuits;2024 IEEE 42nd VLSI Test Symposium (VTS);2024-04-22
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