1. S. M. Sze. Physics of Semiconductor Devices, 2nd ed. (Wiley, New York, 1981).
2. R. E. Matick, S. E. Schuster, “Logic-based eDRAM: Origins and rationale for use,” IBM J. Res. Develop. 49, No. 1, 145 (Jan. 2005), DOI: 10.1147/rd.491.0145.
3. J. Barth, W. R. Reohr, P. Parries, G. Fredeman, J. Golz, S. E. Schuster, Richard E. Matick, H. Hunter, C. C. Tanner, J. Harig, H. Kim, B. A. Khan, J. Griesemer, R. P. Havreluk, K. Yanagisawa, T. Kirihata, S. S. Iyer, “A 500 MHz random cycle, 1.5 ns latency, SOI embedded DRAM macro featuring a three-transistor micro sense amplifier,” IEEE J. Solid-State Circuits 43, No. 1, 86 (Jan. 2008), DOI: 10.1109/JSSC.2007.908006.
4. W. K. Luk, Jin Cai, R. H. Dennard, M. J. Immediato, S. V. Kosonocky, “A 3-transistor DRAM cell with gated diode for enhanced speed and retention time,” Proc. of IEEE Symp. on VLSI Circuits: Honolulu, HI: Digest of Technical Papers (IEEE, 2006), pp. 184–185, DOI: 10.1109/VLSIC.2006.1705371.
5. Ki Chul Chun, P. Jain, Jung Hwa Lee, C. H. Kim, “A sub-0.9V logic-compatible embedded DRAM with boosted 3T gain cell, regulated bit-line write scheme and PVT-tracking read reference bias,” Proc. of IEEE Symp. on VLSI Circuits, 16–18 June 2009, Kyoto, Japan (IEEE, 2009), pp. 134–135, http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=5205419&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D5205419.