A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier-Reference-Cited by-同舟云学术

A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier

Published:2008-01 Issue:1 Volume:43 Page:86-95
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Barth John,Reohr William R.,Parries Paul,Fredeman Gregory,Golz John,Schuster Stanley E.,Matick Richard E.,Hunter Hillery,Tanner Charles C.,Harig Joseph,Kim Hoki,Khan Babar A.,Griesemer John,Havreluk Robert P.,Yanagisawa Kenji,Kirihata Toshiaki,Iyer Subramanian S.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/4443178/04443182.pdf?arnumber=4443182

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