CAD Layout Analysis for Defect Inspection in Semiconductor Fabrication-Reference-Cited by-同舟云学术

CAD Layout Analysis for Defect Inspection in Semiconductor Fabrication

Published:2018-10-09 Issue:5 Volume:66 Page:677-684
ISSN:0377-2063
Container-title:IETE Journal of Research
language:en
Short-container-title:IETE Journal of Research

Author:

Vikram Abhishek¹,Agarwal Vineeta¹,Agarwal Anshul²

Affiliation:

1. Department of Electrical Engineering, Motilal Nehru National Institute of Technology, Allahabad, India

2. Department of Electrical & Electronics, National Institute of Technology Delhi, Delhi, India

Publisher

Informa UK Limited

Subject

Electrical and Electronic Engineering,Computer Science Applications,Theoretical Computer Science

Link

https://www.tandfonline.com/doi/pdf/10.1080/03772063.2018.1517617

Reference27 articles.

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2. Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings

3. Feasibility Study of Process Integration for High Aspect Ratio Hard-Mask Scheme Technologies of Low-k/Cu Interconnect Fabrication

4. Some Thoughts on the IC Design-Manufacture Interface

5. A. Burmen, J. Puhan, and T. Tuma, “Robust design and optimization of operating amplifiers,” Industrial Technology, 2003 IEEE International Conference, Vol. 2, pp. 745–50, Dec. 2003.

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