Node Voltage and KCL Model-Based Low Leakage Volatile and Non-Volatile 7T SRAM Cells

Author:

Kumar C. S. Hemanth1,Kariyappa B. S.2

Affiliation:

1. Department of E&C, Government Engineering College, Ramangara 562159, India

2. Department of E&C, R V College of Engineering, Bengaluru 560059, India

Publisher

Informa UK Limited

Subject

Electrical and Electronic Engineering,Computer Science Applications,Theoretical Computer Science

Reference27 articles.

1. Design of Self Controllable Voltage Level Circuit SVL for Low Power and High Speed 12t Sram at 15nm Technology

2. P. Shukla, et al. “A robust 13T single ended Schmitt trigger based SRAM cell”, in 5th IEEE International Conference on Signal Processing, Computing and Control (ISPCC 2k19), JUIT, Solan, India, 978-1-7281-3988-3/19.

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1. Store and Restore Delay Reduction Techniques of Non-volatile SRAM cells;2023 International Conference on Sustainable Computing and Smart Systems (ICSCSS);2023-06-14

2. Process invariant Schmitt Trigger non-volatile 13T1M SRAM cell;Microelectronics Journal;2023-05

3. Schmitt Trigger 12T1M Non-volatile SRAM cell with improved process variation tolerance;AEU - International Journal of Electronics and Communications;2023-04

4. A novel read decoupled 8T1M nvSRAM cell with improved read/write margin;Analog Integrated Circuits and Signal Processing;2022-12-28

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