Store and Restore Delay Reduction Techniques of Non-volatile SRAM cells
Author:
Affiliation:
1. Delhi Technological University,Dept. of ECE,Delhi,India,110042
2. Bharati Vidyapeeth’s College of Engineering,Dept. of ECE,Delhi,India,110063
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10169129/10169119/10169690.pdf?arnumber=10169690
Reference29 articles.
1. Average 7T1R Nonvolatile SRAM With R/W Margin Enhanced for Low-Power Application
2. Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications
3. A Symmetric Novel 8T3R Non-Volatile SRAM Cell for Embedded Applications
4. Multiple Sharing 7T1R Nonvolatile SRAM With an Improved Read/Write Margin and Reliable Restore Yield
5. Node Voltage and KCL Model-Based Low Leakage Volatile and Non-Volatile 7T SRAM Cells
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