A Precise Design for Testing High-Speed Embedded Memory using a BIST Circuit-Reference-Cited by-同舟云学术

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A Precise Design for Testing High-Speed Embedded Memory using a BIST Circuit

Published:2017-02-17 Issue:4 Volume:63 Page:473-481
ISSN:0377-2063
Container-title:IETE Journal of Research
language:en
Short-container-title:IETE Journal of Research

Author:

Zhang Lijun¹,Wang Ziou²,Li Youzhong¹³,Mao Lingfeng¹

Affiliation:

1. School of Urban Rail Transportation, Soochow University, Jiangsu, P. R. China

2. School of Electronic and Information Engineering, Soochow University, Jiangsu, P. R. China

3. Key Laboratory of Microelectronic Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, P. R. China

Funder

National Natural Science Foundation of China

Publisher

Informa UK Limited

Subject

Electrical and Electronic Engineering,Computer Science Applications,Theoretical Computer Science

Link

https://www.tandfonline.com/doi/pdf/10.1080/03772063.2017.1285259

Reference25 articles.

1. Process variation in embedded memories: failure analysis and variation aware architecture

2. Efficient tests for realistic faults in dual-port SRAMs

3. A new testing acceleration chip for low-cost memory tests

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Optimal Method for Test and Repair Memories Using Redundancy Mechanism for SoC;Micromachines;2021-07-10

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