1. Design and experimental technology for 0.1-µm gate-length low-temperature operation FET's
2. Horiguchi, M., Sakata, T., Sekiguchi, T., Ueda, S., Tanaka, H., Yamasaki, E., Nakagome, Y., Aoki, M., Kaga, T., Ohkura, M., Nagai, R., Murai, F., Tanaka, T., Iijima, S., Yokoyama, N., Gotoh, Y., Shoji, K., Kisu, T., Yamashita, H., Nishida, T. and Takeda, E. Conf. Int. Solid-state Circuits. pp.252 Digest of Technical Papers
3. Sugibayashi, T., Naritake, I., Utsugi, S., Shibahara, K., Oikawa, R., Mori, H., Iwao, S., Murotani, T., Koyama, K., Fukazawa, S., Itani, T., Kasama, K., Okuda, T., Ohya, S. and Ogawa, M. Conf. Int. Solid-state Circuits. pp.254 Digest of Technical Papers
4. Seidel, T. E. 1994 Int. Symp. Semiconductor Manufacturing. Tokyo. pp.14