A CNFET-based hybrid multi-threshold 1-bit full adder design for energy efficient low power applications-Reference-Cited by-同舟云学术

A CNFET-based hybrid multi-threshold 1-bit full adder design for energy efficient low power applications

Published:2018-06-12 Issue:10 Volume:105 Page:1753-1768
ISSN:0020-7217
Container-title:International Journal of Electronics
language:en
Short-container-title:International Journal of Electronics

Author:

Maleknejad Mojtaba¹,Mohammadi Somayyeh²,Navi Keivan³,Naji Hamid Reza⁴,Hosseinzadeh Mehdi⁵⁶

Affiliation:

1. Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran

2. Department of Electrical Engineering, Payame Noor University (PNU), Kerman, Iran

3. Faculty of Electrical and Computer Engineering, Shahid Beheshti University, G.C., Tehran, Iran

4. Faculty of Electrical and Computer Engineering, Graduate University of Advanced Technology, Kerman, Iran

5. Iran University of Medical Sciences, Tehran, Iran

6. Computer Science, University of Human Development, Sulaimaniyah, Iraq

Publisher

Informa UK Limited

Subject

Electrical and Electronic Engineering

Link

https://www.tandfonline.com/doi/pdf/10.1080/00207217.2018.1477205

Reference27 articles.

1. VLSI implementations of threshold logic- a comprehensive survey

2. Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit

3. Adder Designs and Analyses for Quantum-Dot Cellular Automata

4. Deng, J., Device modeling and circuit performance evaluation for nanoscale devices: Silicon technology beyond 45 nm node and carbon nanotube field effect transistors. Doctoral Dissertation, Stanford University, 2007

5. A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region

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