Energy-Efficient Exact and Approximate CNTFET-Based Ternary Full Adders
Author:
Publisher
Springer Science and Business Media LLC
Subject
Applied Mathematics,Signal Processing
Link
https://link.springer.com/content/pdf/10.1007/s00034-023-02589-8.pdf
Reference34 articles.
1. E. Abbasian, A. Aminzadeh, S.T. Anvari, GNRFET- and CNTFET-based designs of highly efficient 22 T unbalanced single-trit ternary multiplier cell. Arab. J. Sci. Eng. (2023). https://doi.org/10.1007/s13369-023-08053-8
2. E. Abbasian, M. Orouji, S.T. Anvari, An efficient GNRFET-based circuit design of ternary half-adder. AEUE – Int. J. Electr. Commun. 170, 154808 (2023). https://doi.org/10.1016/j.aeue.2023.154808
3. S.S. Ahmadpour, M. Mosleh, New designs of fault-tolerant adders in quantum-dot cellular automata. Nano Commun. Netw. 19, 10–25 (2019). https://doi.org/10.1016/j.nancom.2018.11.001
4. N.H. Bastani, M.H. Moaiyeri, K. Navi, An energy and area-efficient approximate ternary adder based on CNTFET switching logic. Circuits, Syst. Signal Process. 37, 1863–1883 (2018). https://doi.org/10.1007/s00034-017-0627-1
5. D. Das, A. Banerjee, V. Prasad. 2018: Design of ternary logic circuits using CNTFET, International Symposium on Devices, Circuits and Systems (ISDCS), (2018). https://doi.org/10.1109/ISDCS.2018.8379661.
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