Design of High-Performance Full Adder Using 20nm CNTFET Technology

Author:

Naveen G.1,Rao V.R Seshagiri1,N Nirmala.1,L Pavan Kalyan.1,Vijay Vallabhuni1,Venkateswarlu S. China1,Vallabhuni Rajeev Ratna2

Affiliation:

1. Institute of Aeronautical Engineering,Department of Electronics and Communications Engineering,Hyderabad,India,500043

2. Bayview Asset Management, LLC,Florida,USA

Publisher

IEEE

Reference25 articles.

1. Mux Based Ultra-Low-Power Ternary Adders and Multiplier implemented with CNFET and 45 nm MOSFETs;vidhyadharan;Int J Elect,2021

2. Two Novel Current-Mode CNFET-Based Full Adders Using ULPD as Voltage Regulator;hamidreza;J of Circ Syst and Comp,2021

3. Ultra-Low Power 8-Transistor Modified Gate Diffusion Input Carbon Nano-Tube Field Effect Transistor Full Adder

4. Design and Implementation of an Efficient VLSI Architecture for 10T Full Adder Used in Ultra Low Power Applications

5. High-Performance 1-Bit Full Adder with Excellent Driving Capability for Multistage Structures;mahmood;IEEE Emb Sys Lett,2021

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1. Design and performance analysis of low power and energy-efficient vedic multipliers;International Journal of System Assurance Engineering and Management;2023-04-29

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