An Energy-Efficient Hybrid Tunnel FET based STT-MRAM Memory Cell Design at Low VDD-Reference-Cited by-同舟云学术

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An Energy-Efficient Hybrid Tunnel FET based STT-MRAM Memory Cell Design at Low VDD

Published:2021-04-26 Issue: Volume: Page:1-16
ISSN:0020-7217
Container-title:International Journal of Electronics
language:en
Short-container-title:International Journal of Electronics

Author:

Yamani Sudha Vani¹^ORCID,Rani N. Usha¹,Vaddi Ramesh²

Affiliation:

1. Department of Electronics and Communication Engineering, Vignan’s Foundation for Science Technology and Research, Guntur, India

2. Department of Electronics and Communication, School of Engineering and Applied Sciences, SRM University, Amaravati, Guntur, India

Publisher

Informa UK Limited

Subject

Electrical and Electronic Engineering

Link

https://www.tandfonline.com/doi/pdf/10.1080/00207217.2021.1914191

Reference32 articles.

1. Implementation of FinFET based STT-MRAM bitcell

2. An Euler–Lagrange Equation Oriented Solution for Write Energy Minimization of STT-MRAM

3. Design Margin Exploration of Spin-Transfer Torque RAM (STT-RAM) in Scaled Technologies

4. Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and 32-Bit CLA Circuits

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Ultralow Voltage FinFET- Versus TFET-Based STT-MRAM Cells for IoT Applications;Electronics;2021-07-22

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