Design of ternary logic gates and buffer- based memory cell in nanoelectronics-Reference-Cited by-同舟云学术

Design of ternary logic gates and buffer- based memory cell in nanoelectronics

Published:2021-11-28 Issue: Volume: Page:1-23
ISSN:0020-7217
Container-title:International Journal of Electronics
language:en
Short-container-title:International Journal of Electronics

Author:

Rahbari Katayoun¹,Hosseini Seied Ali¹^ORCID

Affiliation:

1. Department of Electronic, College of Electrical Engineering, Yadegar-e-Imam Khomeini (RAH) Shahre Rey Branch, Islamic Azad University, Tehran, Iran

Publisher

Informa UK Limited

Subject

Electrical and Electronic Engineering

Link

https://www.tandfonline.com/doi/pdf/10.1080/00207217.2021.2001864

Reference35 articles.

1. Electron Transport and Velocity Oscillations in a Carbon Nanotube

2. Ashewin, D. & Ingole, V. T, and Rojeshrao, V. (2014). Ternary digital system: concepts and applications. www.researchgates.net/publication/266477166.

3. Ternary DDCVSL: a combined dynamic logic style for standard ternary logic with single power source

4. Low power dissipation MOS ternary logic family

5. Design and process variation analysis of CNTFET-based ternary memory cells

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