Highly-Efficient CNTFET-Based Unbalanced Ternary Logic Gates

Abstract

A large number of interconnections required to implement a binary logic-based circuit leads to an increase in power/energy consumption and area overhead. Utilizing multiple-valued logic (MVL), especially ternary logic, can improve power/energy and total area by reducing the number of interconnections. A ternary logic-based circuit is easily implemented by using carbon nanotube field-effect transistors (CNTFETs) because they have the capability of manifesting different threshold voltages. This paper uses CNTFET devices for the design and implementation of highly-efficient ternary logic gates such as the standard ternary inverter (STI), ternary buffer (TBUF), ternary OR (TOR), and ternary AND (TAND). The proposed STI design offers improvement between 12% and 91.17% in energy consumption and increases noise margin by at least 1.02×, while the proposed TBUF design reduces energy consumption by 14.73%–96.82%. Furthermore, the proposed TOR design reduces power dissipation and energy consumption by at least 72.62% and 84.80%, while the proposed TAND design improves them by at least 8.55% and 11.38%, respectively. The simulations have been performed by using HSPICE software with the Stanford 32 nm CNTFET model at 0.9 V supply voltage.