Access-in-turn test architecture for low-power test application-Reference-Cited by-同舟云学术

Access-in-turn test architecture for low-power test application

Published:2016-08-13 Issue:3 Volume:104 Page:433-441
ISSN:0020-7217
Container-title:International Journal of Electronics
language:en
Short-container-title:International Journal of Electronics

Author:

Wang Weizheng¹²,Wang JinCheng¹,Wang Zengyun³,Xiang Lingyun¹²

Affiliation:

1. College of Computer and Communication Engineering, Changsha University of Science and Technology, Changsha, China

2. Hunan Provincial Key Laboratory of Intelligent Processing of Big Data on Transportation, Changsha University of Science and Technology, Changsha, China

3. Department of Mathematics, Hunan First Normal University, Changsha, China

Funder

National Natural Science Foundation of China

Publisher

Informa UK Limited

Subject

Electrical and Electronic Engineering

Link

https://www.tandfonline.com/doi/pdf/10.1080/00207217.2016.1218062

Reference27 articles.

1. Minimizing power consumption in scan testing: pattern generation and DFT techniques

2. A unified approach to reduce soc test data volume, scan power and testing time

3. Jump scan: a DFT technique for low power testing

4. Low-Power Scan Operation in Test Compression Environment

5. Low-Power Test Data Application in EDT Environment Through Decompressor Freeze

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