TCAD performance analysis of a symmetrical double gate non-aligned junction FET device with high and low dielectric gate oxide in sub-100 nm regime
Author:
Affiliation:
1. School of Electronics Engineering, VIT-AP University, Vijayawada, Guntur, Andhra Pradesh, India
Publisher
Informa UK Limited
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Instrumentation,Electronic, Optical and Magnetic Materials
Link
https://www.tandfonline.com/doi/pdf/10.1080/21681724.2023.2173803
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5. International Technology Roadmap for Semiconductors (ITRS). (2010) Edition (2010). Retrieved from http://www.itrs.net.
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1. Impact of underlap layer on DC and RF/analog performance of asymmetric junctionless dual material double gate MOSFET for low-power analog amplifier design;Physica Scripta;2024-08-09
2. Design and test of a sub -45 nm non-aligned double gate inverter in TCAD environment: static and dynamic analysis;International Journal of Electronics Letters;2024-06-27
3. Evaluating Performance Using kϕ Index Parameter for a Symmetrical Junction NADGFET: A 3D TCAD Simulation Analysis;2023 International Conference on Next Generation Electronics (NEleX);2023-12-14
4. Effects of metal work function and gate-oxide dielectric on super high frequency performance of a non-align junction DG-MOSFET based inverter in the sub -100 nm regime: a TCAD simulation analysis;International Journal of Electronics;2023-11-05
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