Parameter extraction and modelling of the MOS transistor by an equivalent resistance

Author:

Sharroush Sherif M.1,Abdalla Yasser S.2

Affiliation:

1. Department of Electrical Engineering, Faculty of Engineering, Port Said University, Port Said, Egypt

2. Department of Computer Engineering and Networks, College of Computer and Information Sciences, Jouf University and Faculty of Industrial Education, Suez University, Suez, Egypt

Publisher

Informa UK Limited

Subject

Applied Mathematics,Computer Science Applications,Modeling and Simulation,Software,Control and Systems Engineering

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. SPICE Modeling of RADFETs with Different Gate Oxide Thicknesses;2023 IEEE 33rd International Conference on Microelectronics (MIEL);2023-10-16

2. Design and Optimization of 4-bit Absolute-value Detector Based on CMOS;Journal of Physics: Conference Series;2023-02-01

3. A Real-Time Electronically Tunable All-MOS Universal Biquadratic Voltage-Mode Filter;Jordan Journal of Electrical Engineering;2023

4. Design and simulation of hybrid SET-CMOS inverter using macro-model technique;Revista Mexicana de Física;2022-11-01

5. Optimum sizing of the sleep transistor in MTCMOS technology;AEU - International Journal of Electronics and Communications;2021-08

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