FOSS EKV2.6 Verilog-A Compact MOSFET Model

Author:

Grabinski Wladek,Abo-Elhadid Ahmed,Mierzwinski Marek,Lemaitre Laurent,Brinson Mike,Lallement Christophe,Sallese Jean-Michel,Yoshitomi Sadayuki,Malisse Paul,Oguey Henri,Cserveny Stefan,Pavanello Marcelo,Enz Christian,Krummenacher Francois,Vittoz Eric,Souza Michelly de,Tomaszewski Daniel,Malesinska Jola,Gluszko Grzegorz,Bucher Matthias,Makris Nikolaos,Nikolaou Aristeidis

Publisher

IEEE

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. FOSS CAD for the Compact Verilog-A Model Standardization in Open Access PDKs;2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM);2024-03-03

2. A 5-DC-parameter MOSFET model for circuit simulation in QucsStudio and SPECTRE;2023 21st IEEE Interregional NEWCAS Conference (NEWCAS);2023-06-26

3. A Compact Model Adopting the EKV Model for a Silicon Vertical Power MOSFET;2021 IEEE Applied Power Electronics Conference and Exposition (APEC);2021-06-14

4. A BSIM-Based Predictive Hot-Carrier Aging Compact Model;2021 IEEE International Reliability Physics Symposium (IRPS);2021-03

5. Parameter extraction and modelling of the MOS transistor by an equivalent resistance;Mathematical and Computer Modelling of Dynamical Systems;2021-01-02

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