FPGA Implementation of Ternary Multiplier Using Reconfigurable Logic
Author:
Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-99-9179-2_27
Reference7 articles.
1. Sharma T, Kumre L (2020) Energy-efficient ternary arithmetic logic unit design in CNTFET technology. Circ Syst Sig Process 39(7):3265–3288. https://doi.org/10.1007/s00034-019-01318-4
2. Sahoo SK, Akhilesh G, Sahoo R, Mugkilar M (2017) High performance ternary adder using CNTFET. IEEE Trans Nanotechnol 16(3)
3. Tabrizchi S, Azimi N, Navi K (2017) A novel ternary half adder and multiplier based on carbon nanotube field effect transistors. J Zhejiang Univ Sci C 18(3):423–433. https://doi.org/10.1631/FITEE.1500366
4. Kim S, Lee S-Y, Park S, Kim KR, Kang S (2020) A logic synthesis methodology for low-power ternary logic circuits. IEEE Trans Cir Syst I Regul Pap 67(9):3138–3151. [Online]. Available: https://ieeexplore.ieee.org/document/9089220/56734
5. Shahrom E, Hosseini SA (2018) ‘A new low power multiplexer based ternary multiplier using CNTFETs. AEU Int J Electron Commun 93:191–207. https://doi.org/10.1016/j.aeue.2018.06.011
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